The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Aug. 13, 2018
Applicant:
Renesas Electronics America Inc., Milpitas, CA (US);
Inventors:
Tetsuo Sato, San Jose, CA (US);
Koichi Yamazaki, Maebashi, JP;
Assignee:
RENESAS ELECTRONICS AMERICA INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/155 (2006.01); H03K 17/687 (2006.01); H03K 17/567 (2006.01); H03K 17/74 (2006.01); H03K 17/0416 (2006.01); H02M 7/00 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H03K 17/04163 (2013.01); H03K 17/567 (2013.01); H03K 17/74 (2013.01); H02M 7/003 (2013.01); Y02B 70/1483 (2013.01);
Abstract
An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect transistor (JFET), a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET, and a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET. An inductor input terminal is connected to the drain of the first SiC JFET.