The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Jul. 22, 2016
Applicant:
Abb Schweiz Ag, Baden, CH;
Inventors:
Pietro Cairoli, Raleigh, NC (US);
Lukas Hofstetter, Basel, CH;
Matthias Bator, Klettgau, DE;
Riccardo Bini, Baden, CH;
Munaf Rahimo, Uezwil, CH;
Assignee:
ABB Schweiz AG, Baden, CH;
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/567 (2006.01); H03K 17/687 (2006.01); H02H 7/00 (2006.01); H03K 17/10 (2006.01); H03K 17/12 (2006.01); H02H 3/02 (2006.01);
U.S. Cl.
CPC ...
H03K 17/567 (2013.01); H02H 7/005 (2013.01); H03K 17/6872 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/49113 (2013.01); H02H 3/023 (2013.01); H03K 17/102 (2013.01); H03K 17/122 (2013.01); H03K 17/125 (2013.01); H03K 2017/6875 (2013.01); H03K 2217/0036 (2013.01);
Abstract
A solid state switch has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. The at least one FET-type device is constructed with a first power loss profile based on a rated current of an electrical device; and the at least one thyristor-type device is constructed with a second power loss profile based on a surge current associated with the electrical device.