The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Apr. 07, 2016
Jae-hwan Lee, Seoul, KR;
Sangsu Kim, Yongin-si, KR;
Sanghyuk Hong, Yongin-si, KR;
Seung MO Ha, Seoul, KR;
Jae-Hwan Lee, Seoul, KR;
Sangsu Kim, Yongin-si, KR;
Sanghyuk Hong, Yongin-si, KR;
Seung Mo Ha, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.