The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Jul. 13, 2018
Qualcomm Incorporated, San Diego, CA (US);
Mustafa Badaroglu, Kessel-Lo, BE;
Kern Rim, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods are disclosed. At least a portion of the dielectric layers and/or work function metal layers present in active gate(s) is not present in a field gate(s) of a gate in a circuit cell. The field gate(s) have more conductive gate material than the active gate(s). In this manner, the increased volume of gate material in the field gate(s) reduces gate layout parasitic resistance. The active gate(s) retains the dielectric layers and/or work function metal layers to effectively isolate the gate material from a channel of a FET formed from the circuit cell to provide effective channel control. Reducing gate layout parasitic resistance can reduce current (I) resistance (R) (IR) drop to achieve the desired drive strength in the integrated circuit.