The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10411056 B1

Date of Patent:

Sep. 10, 2019

Filed:

Oct. 19, 2016

Semiconductor device and manufacturing method of the same

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Koji Iizuka, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Su C Kim

Int. Cl.

CPC ...

H01L 27/146 (2006.01); H01L 23/00 (2006.01);

U.S. Cl.

CPC ...

H01L 27/1462 (2013.01); H01L 23/564 (2013.01); H01L 27/14601 (2013.01); H01L 27/14603 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14683 (2013.01); H01L 27/14685 (2013.01); H01L 27/14687 (2013.01); H01L 27/146 (2013.01); H01L 27/14621 (2013.01);

Abstract

There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region.

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