The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Jun. 07, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Woo Jin Jang, Suwon-si, KR;

Young Jin Noh, Suwon-si, KR;

Jun Kyu Yang, Seoul, KR;

Bio Kim, Seoul, KR;

Kyong Won An, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/51 (2006.01); H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0223 (2013.01); H01L 21/28282 (2013.01); H01L 21/3115 (2013.01); H01L 21/31111 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/513 (2013.01); H01L 27/11565 (2013.01); H01L 29/518 (2013.01);
Abstract

An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.


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