The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Dec. 14, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Thomas Kuenemund, Munich, DE;

Mayk Roehrich, Dresden, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); G06F 21/72 (2013.01); H01L 21/8238 (2006.01); G06F 21/00 (2013.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 23/576 (2013.01); G06F 21/72 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); G06F 21/00 (2013.01); H01L 21/823871 (2013.01); H01L 2027/11838 (2013.01);
Abstract

According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.


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