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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10410946 B1

PDFFull Text
Date of Patent:
Sep. 10, 2019

Filed:

Jan. 15, 2018

Semiconductor device

Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Naohito Suzumura, Tokyo, JP;

Hideki Aono, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

Shapiro, Gabor and Rosenberger, PLLC

Primary Examiner:

Hung K Vu

Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 23/367 (2006.01); H01L 23/528 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/76895 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 23/50 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 27/11807 (2013.01); H01L 27/0211 (2013.01); H01L 2027/11874 (2013.01);
Abstract

A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

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