The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Apr. 20, 2018
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Chenglong Zhang, Shanghai, CN;

Haiyang Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/0276 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/76805 (2013.01); H01L 21/76819 (2013.01); H01L 21/76829 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 23/535 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H01L 27/0886 (2013.01);
Abstract

A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the gate structures. Sidewall spacers are formed on side surfaces of the gate structures and the protective layer. A first dielectric layer is formed on the surface of the semiconductor substrate and covering the fins and the side surfaces of the sidewall spacers. A mask layer is formed on a portion of the first dielectric layer between adjacent gate structures. The mask layer and the protective layer are formed by etching a mask material layer. A second dielectric layer is formed on the first dielectric layer, the protective layer and the sidewall spacers and covering the side surfaces of the mask layer. Conductive vias are formed in the first dielectric layer between the adjacent gate structures and at both sides of the mask layer.


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