The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Apr. 03, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventor:

Yoshikazu Katoh, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); G11C 7/24 (2006.01); H01L 45/00 (2006.01); G11C 7/20 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 7/24 (2013.01); G11C 13/0007 (2013.01); G11C 13/0059 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); H01L 27/2463 (2013.01); G11C 7/20 (2013.01); G11C 2013/0076 (2013.01); G11C 2013/0083 (2013.01); G11C 2213/15 (2013.01); G11C 2213/32 (2013.01); G11C 2213/79 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01);
Abstract

A non-volatile memory device comprises a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.


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