The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Mar. 06, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Akira Katayama, Yokohama Kanagawa, JP;

Katsuyuki Fujita, Nishitokyo Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 11/1653 (2013.01); G11C 11/1675 (2013.01); G11C 11/2253 (2013.01); G11C 11/2273 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 11/161 (2013.01); G11C 2013/0054 (2013.01); G11C 2207/002 (2013.01);
Abstract

A memory includes a bit line connected to a memory cell and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell, a first transistor to control a current supplied to the memory cell based on a first control signal, and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.


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