The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Aug. 22, 2018
Ningbo University, Zhejiang, CN;
Pengjun Wang, Zhejiang, CN;
Keji Zhou, Zhejiang, CN;
Yuejun Zhang, Zhejiang, CN;
Huihong Zhang, Zhejiang, CN;
Ningbo University, Zhejiang, CN;
Abstract
A static memory cell capable of balancing bit line leakage currents is characterized by including a 1PMOS transistor, a 2PMOS transistor, a 1NMOS transistor, a 2NMOS transistor, a 3NMOS transistor, a 4NMOS transistor, a 5NMOS transistor, a 6NMOS transistor, a 7NMOS transistor, an 8NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1NMOS transistor, the 2NMOS transistor, the 3NMOS transistor and the 4NMOS transistor are all normal threshold NMOS transistors. The 1PMOS transistor and the 2PMOS transistor are both low threshold PMOS transistors. The 5NMOS transistor, the 6NMOS transistor, the 7NMOS transistor and the 8NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.