The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Jan. 30, 2015
Applicant:

Lapis Semiconductor Co., Ltd., Yokohama, JP;

Inventor:

Hiroaki Ishii, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/3275 (2016.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/3685 (2013.01); G09G 3/3275 (2013.01); G09G 2310/0272 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2352/00 (2013.01);
Abstract

First to N-th latches capture N pieces of pixel data indicative of the luminance levels of respective pixels in synchronization with first to N-th capture clock signals each having different edge timing. Voltages corresponding to the pieces of pixel data output from the first to N-th latches are applied to each of the data lines of the display device. In this case, first to N-th flip-flops formed in an N-stage shift register capture a single pulse load signal which is synchronized with a horizontal synchronizing signal in a video signal while sequentially shifting the load signal to subsequent stages in synchronization with a reference timing signal supplied from the outside. Outputs of the first to N-th flip-flops in the N-stage shift register are supplied as first to N-th capture clock signals, to the first to N-th latches, respectively.


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