The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Jul. 04, 2018
Applicant:

Asmedia Technology Inc., New Taipei, TW;

Inventor:

Kuo-Lung Li, New Taipei, TW;

Assignee:

ASMEDIA TECHNOLOGY INC., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01);
Abstract

A bridge device includes a first physical layer circuit, a first buffer memory, a DMA controller, and a processor. The first physical layer circuit is configured to connect to an upstream device. The first buffer memory is configured to store a first data and transfer data to the upstream device via the first physical layer circuit. The DMA controller is coupled to the first buffer memory and configured to access the first data in the first buffer memory to read and/or write a storage device correspondingly. The processor is coupled to the first buffer memory and the DMA controller. When the bridge device receives a clear feature command from the upstream device, the processor is configured to reset the first buffer memory and the DMA controller to stop the data transferring between the upstream device and the bridge device.


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