The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Apr. 10, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Sung-Hwan Bae, Seoul, KR;

Chan-Ik Park, Suwon-si, KR;

Hyun-Jin Choi, Suwon-si, KR;

Seong-Jun Ahn, Seoul, KR;

In-Hwan Doh, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/02 (2006.01); G06F 12/0873 (2016.01); G06F 12/1036 (2016.01); G06F 12/14 (2006.01); G06F 21/78 (2013.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); G06F 12/0873 (2013.01); G06F 12/1036 (2013.01); G06F 12/1408 (2013.01); G06F 21/78 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7207 (2013.01);
Abstract

In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.


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