The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Sep. 29, 2017
Applicant:

Georgios Fainekos, Phoenix, AZ (US);

Inventor:

Georgios Fainekos, Phoenix, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 11/36 (2006.01); G06F 17/50 (2006.01); G06F 9/448 (2018.01); G06F 16/901 (2019.01);
U.S. Cl.
CPC ...
G06F 11/3608 (2013.01); G06F 9/4498 (2018.02); G06F 11/3604 (2013.01); G06F 11/3676 (2013.01); G06F 11/3684 (2013.01); G06F 11/3696 (2013.01); G06F 16/9024 (2019.01); G06F 17/5009 (2013.01);
Abstract

One embodiment is a methodology for model verification. An embodiment obtaining, by a processor, a model for a system; identifying, by the processor, at least one block within the model that has a branching structure; identifying, by the processor, at least one model variable affecting a switching condition of the identified at least one block; generating, by the processor, an extended finite state machine modeling a switching behavior of the identified at least one block by using the at least one model variable; combining, by the processor, at least one output variable of the extended finite state machine with at least one of a first output port and a second output port of the system included in the model; and performing, by the processor, model verification and coverage of the model that utilizes outputs from the first output port and the second output port to verify the model.


Find Patent Forward Citations

Fainekos, Georgios. (2019). Automated test generation for structural coverage for temporal logic falsification of cyber-physical systems (U.S. Patent No. 10409706). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10409706

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…