The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Mar. 09, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventor:

Keita Kimura, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0614 (2013.01); G06F 3/0629 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 11/5635 (2013.01); G11C 16/10 (2013.01); G06F 2212/214 (2013.01); G11C 2213/71 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a memory string including first and second selection transistors, a first transistor, and first and second memory cell transistors, first and second selection gate lines, first to third word lines, and a row decoder. A write operation includes a first mode to write one-bit data and a second mode to write two-bit data. In a case of writing the one-bit data to the first memory cell transistor in the first mode, the row decoder applies a first voltage to the first word line. In a case of writing the two-bit data to the first memory cell transistor in the second mode, the row decoder applies, to the first word line, a second voltage that is higher than the first voltage.


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