The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Mar. 01, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Manabu Matsumoto, Yokahama Kanagawa, JP;

Katsuya Murakami, Sumida Tokyo, JP;

Akira Tanimoto, Yokohama Kanagawa, JP;

Isao Ozawa, Chigasaki Kanagawa, JP;

Yuji Karakane, Nagoya Aichi, JP;

Tadashi Shimazaki, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/04 (2006.01); G06F 1/18 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 29/12 (2006.01); G11C 16/06 (2006.01); G11C 29/48 (2006.01); H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); G11C 29/04 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G06F 1/183 (2013.01); G11C 7/04 (2013.01); G11C 16/06 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 29/12 (2013.01); G11C 29/1201 (2013.01); G11C 29/48 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); G11C 2029/0401 (2013.01); G11C 2029/5602 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/34 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48235 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/141 (2013.01); H01L 2924/1425 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/3011 (2013.01);
Abstract

A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.


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