The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Aug. 31, 2018
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Hironori Sato, Kawasaki Kanagawa, JP;

Hiroaki Muraoka, Kawasaki Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0016 (2013.01); H01L 27/0207 (2013.01);
Abstract

A device for automatic configuration of a semiconductor integrated circuit includes a memory that stores circuit data representing a structure of a logic circuit including a first clock gating circuit, and a processor. The processor is configured to retrieve the circuit data from the memory, determine first and second logical elements from each of which an enable signal is output to the first clock gating circuit, calculate a delay time of each of the first and second logical elements, separate the first and second logical elements on the basis of the calculated delay time, and add a second clock gating circuit for the first logical element after separating the first and second logical elements.


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