The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2019
Filed:
Sep. 04, 2018
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/304 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/205 (2013.01); H01L 21/0254 (2013.01); H01L 21/304 (2013.01); H01L 21/31053 (2013.01); H01L 21/31056 (2013.01); H01L 21/76229 (2013.01); H01L 29/2003 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 29/1066 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01); H01L 29/7786 (2013.01);
Abstract
In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.