The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Jul. 12, 2017
Applicant:

Meridian Innovation Pte Ltd, Singapore, SG;

Inventors:

Piotr Kropelnicki, Singapore, SG;

Ilker Ender Ocak, Singapore, SG;

Paul Simon Pontin, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 27/146 (2006.01); G01J 5/04 (2006.01); B81C 1/00 (2006.01); G01J 5/02 (2006.01); G01J 5/12 (2006.01); G01J 5/08 (2006.01); G01J 5/16 (2006.01); H01L 31/0224 (2006.01); H01L 31/09 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14669 (2013.01); B81C 1/00 (2013.01); G01J 5/024 (2013.01); G01J 5/0225 (2013.01); G01J 5/046 (2013.01); G01J 5/048 (2013.01); G01J 5/0853 (2013.01); G01J 5/12 (2013.01); G01J 5/16 (2013.01); H01L 27/146 (2013.01); H01L 27/14612 (2013.01); H01L 27/14629 (2013.01); H01L 27/14643 (2013.01); H01L 27/14649 (2013.01); H01L 31/0224 (2013.01); H01L 31/09 (2013.01); G01J 2005/123 (2013.01);
Abstract

Device and method of forming the devices are disclosed. The method includes providing a substrate prepared with transistor and sensor regions. The substrate is processed by forming a lower sensor cavity in the substrate, filling the lower sensor cavity with a sacrificial material, forming a dielectric membrane in the sensor region, forming a transistor in the transistor region and forming a micro-electrical mechanical system (MEMS) component on the dielectric membrane in the sensor region. The method continues by forming a back-end-of-line (BEOL) dielectric having a plurality of interlayer dielectric (ILD) layers with metal and via levels disposed on the substrate for interconnecting the components of the device. The metal lines in the metal levels are configured to define an upper sensor cavity over the lower sensor cavity, and metal lines of a first metal level of the BEOL dielectric are configured to define a geometry of the MEMS component.


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