The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

May. 29, 2014
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Heecheol Kim, Beijing, CN;

Youngsuk Song, Beijing, CN;

Seongyeol Yoo, Beijing, CN;

Seungjin Choi, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 29/66 (2006.01); H01L 23/528 (2006.01); H01L 21/56 (2006.01); H01L 21/441 (2006.01); H01L 29/24 (2006.01); H01L 23/522 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1248 (2013.01); H01L 21/441 (2013.01); H01L 21/56 (2013.01); H01L 21/76831 (2013.01); H01L 23/3171 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1259 (2013.01); H01L 27/1262 (2013.01); H01L 29/24 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78603 (2013.01); H01L 29/78636 (2013.01); H01L 29/78696 (2013.01); H01L 2224/08052 (2013.01); H01L 2924/13069 (2013.01);
Abstract

An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes: a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate; a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes. The array substrate further includes: a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer and the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT.


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