The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

May. 25, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sung-Min Hwang, Hwaseong-si, KR;

Joon-Sung Lim, Seongnam-si, KR;

Gilsung Lee, Seoul, KR;

Eunsuk Cho, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11573 (2017.01); G11C 16/24 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); G11C 16/24 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.


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