The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Oct. 10, 2017
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Jan Van Houdt, Bekkevoort, BE;

Julien Ryckaert, Schraerbeek, BE;

Hyungrock Oh, Leuven, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 5/02 (2006.01); H01L 23/528 (2006.01); H01L 27/108 (2006.01); G11C 11/405 (2006.01); H01L 21/8254 (2006.01); G11C 11/4097 (2006.01); G11C 13/00 (2006.01); G11C 5/04 (2006.01); H01L 25/065 (2006.01); G11C 11/4076 (2006.01); H01L 49/02 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
H01L 27/108 (2013.01); G11C 11/405 (2013.01); G11C 11/4097 (2013.01); H01L 21/8254 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 11/4076 (2013.01); G11C 11/4094 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/71 (2013.01); H01L 23/528 (2013.01); H01L 25/0657 (2013.01); H01L 27/10805 (2013.01); H01L 28/60 (2013.01);
Abstract

The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.


Find Patent Forward Citations

Loading…