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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10403620 B1

PDFFull Text
Date of Patent:
Sep. 03, 2019

Filed:

Jan. 12, 2017

Semiconductor device

Applicant:

Hitachi Automotive Systems, Ltd., Hitachinaka-shi, Ibaraki, JP;

Inventors:

Shinichirou Wada, Tokyo, JP;

Katsumi Ikegaya, Hitachinaka, JP;

Assignee:

HITACHI AUTOMOTIVE SYSTEMS, LTD., Hitachinaka-Shi, JP;

Attorney:

Foley & Lardner LLP

Primary Examiner:

George R Fourson, III

Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/12 (2006.01); H01L 27/088 (2006.01); H01L 21/762 (2006.01); H03K 17/082 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/76224 (2013.01); H01L 27/088 (2013.01); H01L 27/1203 (2013.01); H01L 27/0211 (2013.01); H01L 27/0266 (2013.01); H01L 29/7393 (2013.01); H03K 17/0822 (2013.01);
Abstract

To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor. A high-side NMOS transistoris formed in a region Son the surface of a SOI substrate. A trenchsurrounds the high-side NMOS transistor. SiO(first insulator) embeds the trench. A low-side NMOS transistoris formed in a region Son the surface of the SOI substratearound the trench. The side face Sf connecting the region Sforming the low-side NMOS transistortherein and the backside of the SOI substrateis exposed.

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