Repair circuit used in a memory device for performing error correction code operation and redundancy repair operation

Abstract

Disclosed is a memory device including a plurality of memory cell arrays each of which includes a normal cell array and a redundant cell array, a first fuse unit including a plurality of first fuse sets corresponding to first memory cell arrays among the memory cell arrays, a second fuse unit including a plurality of second fuse sets corresponding to second memory cell arrays among the memory cell arrays, the first fuse sets corresponding to the second fuse sets, respectively, and a repair unit selecting a pair of fuse sets that correspond to each other from the first fuse sets and the second fuse sets based on information that represents whether each of the first fuse sets and the second fuse sets failed or is usable and programming a repair target column address of the memory cell arrays in the selected fuse set pair.