The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2019
Filed:
Mar. 02, 2018
Toshiba Memory Corporation, Minato-ku, Tokyo, JP;
Nobuhiro Tsuji, Yokohama Kanagawa, JP;
Hiroki Ohkouchi, Yokohama Kanagawa, JP;
Shota Note, Yokohama Kanagawa, JP;
Masashi Nakata, Yokohama Kanagawa, JP;
Yohei Yasuda, Yokohama Kanagawa, JP;
TOSHIBA MEMORY CORPORATION, Tokyo, JP;
Abstract
A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.