The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Oct. 18, 2017
Applicant:

Aspiring Sky Co., Limited, Hong Kong, CN;

Inventors:

Zhijiong Luo, Hopewell Township, PA (US);

Xiaoming Jin, Shanghai, CN;

Shu Wang, Shanghai, CN;

Assignee:

Aspiring Sky Co., Limited, Hong Kong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 3/06 (2006.01); H03K 19/177 (2006.01); G11C 16/04 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 3/0604 (2013.01); G06F 3/0632 (2013.01); G06F 3/0679 (2013.01); H03K 19/17728 (2013.01); G06F 2212/202 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 16/0425 (2013.01); G11C 16/0466 (2013.01); G11C 2207/2245 (2013.01); G11C 2213/79 (2013.01);
Abstract

Technologies are described for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.


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