The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2019

Filed:

Mar. 29, 2018
Applicant:

Korea Institute of Science and Technology, Seoul, KR;

Inventors:

Young In Jhon, Seoul, KR;

Young Tae Byun, Seoul, KR;

Yong Tae Kim, Seoul, KR;

Young Min Jhon, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 27/414 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G01N 27/4146 (2013.01); G01N 27/414 (2013.01); G01N 27/4145 (2013.01); H01L 21/823462 (2013.01); H01L 27/0886 (2013.01); H01L 27/1203 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Provided are a method of fabricating a 3-dimensional transistor sensor and the sensor and a sensor array thereof. The method of fabricating the 3-dimensional transistor sensor includes forming an insulating layer on a silicon substrate, forming a silicon layer on the insulating layer and forming a 3-dimensional silicon fin by etching the silicon layer, forming a source area and a source electrode at one end of the silicon fin, forming a drain area and a drain electrode at the other end the silicon fin, and forming a gate area at a center of the silicon fin, surrounding three surfaces of a gate with a gate insulating layer, forming a sensing gate layer configured to surround a portion of the gate insulating layer, and sealing an upper portion of the gate insulating layer excluding the sensing gate layer.


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