The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Mar. 25, 2016
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventors:

Seiji Goto, Nagaokakyo, JP;

Takahiro Hirao, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 13/00 (2006.01); H01G 4/30 (2006.01); H01G 13/00 (2013.01); H01G 4/12 (2006.01); H03H 3/02 (2006.01); H03H 3/08 (2006.01);
U.S. Cl.
CPC ...
H05K 13/00 (2013.01); H01G 4/12 (2013.01); H01G 4/30 (2013.01); H01G 13/00 (2013.01); H05K 13/0015 (2013.01); H05K 13/0092 (2013.01); H03H 3/02 (2013.01); H03H 3/08 (2013.01);
Abstract

A method for manufacturing an electronic component, and a device for manufacturing the electronic component, which can easily achieve alignment by inserting multilayer chips into cavities formed in a pallet, and form external electrodes with a high degree of dimensional accuracy. A plurality of multilayer chips each composed of a laminated body with a plurality of ceramic layers and a plurality of internal electrode layers is inserted into each of a plurality of cavities formed in a pallet, and the plurality of multilayer chips is aligned by moving each of the plurality of multilayer chips to one of inner wall surfaces forming the cavity. A conductive ink is applied onto ends of the plurality of aligned multilayer chips, including the upper surface of the pallet, and the conductive ink applied is dried to form external electrodes on the plurality of multilayer chips.


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