The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Jul. 14, 2016
Applicant:

Nippon Telegraph and Telephone Corporation, Tokyo, JP;

Inventors:

Saki Hatta, Tokyo, JP;

Tomoaki Kawamura, Tokyo, JP;

Kenji Kawai, Tokyo, JP;

Nobuyuki Tanaka, Tokyo, JP;

Satoshi Shigematsu, Tokyo, JP;

Namiko Ikeda, Tokyo, JP;

Shoko Ohteru, Tokyo, JP;

Junichi Kato, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/40 (2013.01); H04B 10/50 (2013.01); H04B 10/60 (2013.01); H04L 12/44 (2006.01); H04Q 11/00 (2006.01); H04L 12/911 (2013.01);
U.S. Cl.
CPC ...
H04L 47/788 (2013.01); H04L 12/44 (2013.01); H04Q 11/0067 (2013.01); H04B 10/40 (2013.01); H04B 10/50 (2013.01); H04B 10/60 (2013.01); H04Q 2011/0086 (2013.01);
Abstract

An upstream allocation circuit () and a downstream allocation circuit () are provided in an OLT (). For example, a superimposed frame obtained by bundling upstream frames (upstream control frames+upstream data frames) from all ONUS is input to the upstream allocation circuit () via a frame reproduction circuit (-). The superimposed frame may be generated at the stage of optical signals or generated after converting optical signals into electrical signals. The upstream allocation circuit () allocates each of the upstream control frames bundled into the superimposed frame to a predetermined PON control circuit () based on information (PON port number or LLID) added to the frames. The downstream allocation circuit () allocates, to a preset frame reproduction circuit (), each downstream control frames output from the PON control circuits ().


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