The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

May. 20, 2016
Applicants:

Nikolaos Papadopoulos, Kitchener, CA;

Manoj Sachdev, Waterloo, CA;

William Wong, Waterloo, CA;

Inventors:

Nikolaos Papadopoulos, Kitchener, CA;

Manoj Sachdev, Waterloo, CA;

William Wong, Waterloo, CA;

Assignee:

Other;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0944 (2006.01); H03K 19/094 (2006.01); G09G 3/20 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H03K 17/687 (2006.01); G09G 3/34 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0944 (2013.01); G09G 3/20 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 29/7869 (2013.01); H01L 29/78663 (2013.01); H03K 17/6871 (2013.01); H03K 19/094 (2013.01); G09G 3/344 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0289 (2013.01); G09G 2320/0214 (2013.01); G09G 2320/04 (2013.01); G09G 2330/021 (2013.01); G09G 2330/023 (2013.01); H01L 29/24 (2013.01);
Abstract

A unipolar inverter circuit for thin-film transistor circuits including: a driving voltage input; an input signal; a base voltage input; a first stage having a first inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal; a capacitor coupled to the output of the first stage at a node A; and a second stage having: a second inverter circuit having a second stage load transistor and a second stage driving transistor, wherein a gate of the load transistor is connected to the capacitor at a node B; and a clamping transistor connected between the driving voltage and the node B for controlling a voltage, wherein the clamping transistor gate is connected to the driving voltage input; and an output, wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow approximately full voltage swing at the output based on the input signal.


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