The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Jun. 07, 2016
Applicant:

Safran Electrical & Power, Blagnac, FR;

Inventors:

Valery Chau, Evry, FR;

Philippe Preciat, Gourdan, FR;

Pascal Rollins, Daux, FR;

Sonia Dhokkar, Brunoy, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/00 (2006.01); H02M 1/08 (2006.01); H02M 3/337 (2006.01); H02M 1/38 (2007.01); H02M 7/10 (2006.01); B64D 13/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/083 (2013.01); H02M 3/337 (2013.01); B64D 13/00 (2013.01); H02M 1/38 (2013.01); H02M 7/103 (2013.01); H02M 2001/007 (2013.01); H02M 2001/008 (2013.01); H02M 2001/0058 (2013.01); H02M 2001/0067 (2013.01); Y02B 70/1491 (2013.01);
Abstract

The invention relates to an electric DC-DC converter suitable for being supplied with power by a primary voltage source and for supplying control electronics of a three-phase inverter with power, said three-phase inverter being configured to control a fan of a ventilation system of an aircraft. The DC-DC converter is characterised in that it comprises a transformer (), a primary circuit () comprising two loops forming a symmetrical assembly, at least one secondary circuit () comprising a secondary winding (L), suitable for supplying, firstly, the inverter with an output voltage equal to twice the peak voltage at the terminals of the secondary winding (L) and, secondly, a branch of the circuit suitable for supplying the inverter with an output voltage equal to the opposite of the peak voltage at the terminals of the secondary winding (L), and in that the controllable transistors (M, M) are suitable for each being switched at zero voltage.


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