The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

May. 13, 2015
Applicant:

Lg Innotek Co., Ltd., Seoul, KR;

Inventors:

Dae Geun Kim, Seoul, KR;

Kyoung Un Kim, Seoul, KR;

Seul Ki Kim, Seoul, KR;

Bong Kul Min, Seoul, KR;

Gyu Hyeong Bak, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 27/15 (2006.01); H01L 33/62 (2010.01); H01L 25/075 (2006.01); H01L 33/48 (2010.01); H01L 33/64 (2010.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 25/0753 (2013.01); H01L 33/486 (2013.01); H01L 33/64 (2013.01); H01L 2224/48091 (2013.01); H01L 2924/181 (2013.01);
Abstract

An embodiment comprises: a substrate having a chip mounting region; first and second wiring layers disposed on the substrate around the chip mounting region so as to be spaced apart from each other; and a plurality of light emitting chips disposed on the chip mounting region, wherein the first wiring layer comprises a first wiring pattern disposed at one side of a reference line and having a first concave part, and a first extending pattern extending from the first wiring pattern to the other side of the reference line, the second wiring layer comprises a second wiring pattern disposed at the other side of the reference line and having a second concave part, and a second extending pattern extending from the second wiring pattern to one side of the reference line, and the reference line is a straight line passing through the center of the chip mounting region.


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