The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Jul. 09, 2018
Applicant:

Epistar Corporation, Hsinchu, TW;

Inventors:

Chien-Kai Chung, Hsinchu, TW;

Po-Shun Chiu, Hsinchu, TW;

Hsin-Ying Wang, Hsinchu, TW;

De-Shan Kuo, Hsinchu, TW;

Tsun-Kai Ko, Hsinchu, TW;

Yu-Ting Huang, Hsinchu, TW;

Assignee:

Epistar Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/22 (2010.01); H01L 33/38 (2010.01); H01L 33/20 (2010.01); H01L 33/14 (2010.01);
U.S. Cl.
CPC ...
H01L 33/22 (2013.01); H01L 33/20 (2013.01); H01L 33/38 (2013.01); H01L 33/145 (2013.01); H01L 33/382 (2013.01);
Abstract

A light-emitting device includes: a rectangular shape with a first side, a second side opposite to the first side, and a third side connecting the first side and the second side; a light-emitting stack, comprising a lower semiconductor layer, an upper semiconductor layer, and an active layer between the lower semiconductor layer and the upper semiconductor layer; a first electrode formed on the lower semiconductor layer, comprising a first electrode pad and a first extension electrode; a second electrode formed on the upper semiconductor layer, comprising a second electrode pad and a second extension electrode; and a first current blocking layer formed between the lower semiconductor layer and the first electrode pad, wherein the first current blocking layer comprises a top surface and side surfaces; wherein the first electrode pad covers the top surface and the side surfaces of the first current blocking layer and contacts the lower semiconductor layer.


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