The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Jun. 27, 2018
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Ferdinando Iucolano, Gravina di Catania, IT;

Andrea Severino, Aci Sant'Antonio, IT;

Maria Concetta Nicotra, Catania, IT;

Alfonso Patti, Tremestieri Etneo, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 21/28 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7784 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/28264 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/66462 (2013.01); H01L 29/7783 (2013.01); H01L 29/7786 (2013.01);
Abstract

A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.


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