The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Oct. 30, 2017
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Qing Liu, Irvine, CA (US);

Akira Ito, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); H01L 27/0886 (2013.01); H01L 29/1095 (2013.01); H01L 29/42356 (2013.01); H01L 29/7816 (2013.01);
Abstract

A semiconductor device includes a substrate having a first well region comprising a first dopant and a second well region comprising a second dopant. The semiconductor device includes semiconductor fin structures formed on the substrate, where at least one semiconductor fin structure has a channel region along a channel axis through the first well region. The semiconductor device includes a drain region and a source region formed on the semiconductor fin structures. The first well region and the drain region are formed to operate at a first operating voltage, and the second well region and the source region are formed to operate at a second operating voltage that is smaller than the first operating voltage. The semiconductor device includes a gate structure and a dummy gate disposed on respective portions of the semiconductor fin structures, where the dummy gate is disposed between the gate structure and the drain region.


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