The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Dec. 27, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

JongUk Bae, Seoul, KR;

YongHo Jang, Goyang-si, KR;

JunHyeon Bae, Goyang-si, KR;

Kwanghwan Ji, Taebaek-si, KR;

PilSang Yun, Bucheon-si, KR;

Jiyong Noh, Goyang-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1368 (2006.01); H01L 27/32 (2006.01); G02F 1/1362 (2006.01); H01L 29/786 (2006.01); G09G 3/36 (2006.01); G09G 3/3266 (2016.01); G09G 3/3258 (2016.01); G09G 3/3275 (2016.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/1368 (2013.01); G02F 1/136209 (2013.01); G02F 1/136286 (2013.01); H01L 27/3272 (2013.01); H01L 29/41733 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01);
Abstract

Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, and a display panel and a display device using the same, in which a first conductor and a second conductor are provided at end portions of a semiconductor layer formed of oxide semiconductor. The first conductor and second conductor are electrically connected to a first electrode and a second electrode, and covered by a gate insulation layer. The oxide TFT includes a semiconductor layer provided on a buffer and including an oxide semiconductor, a gate insulation layer covering the semiconductor layer and the buffer, a gate electrode provided on the gate insulation layer to overlap a portion of the semiconductor layer, and a passivation layer covering the gate and the gate insulation layer.


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