Vertical memory device and method of manufacturing the same

Abstract

Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.