Semiconductor memory device with plurality of write loops including write and verify operations

Abstract

According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit. The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.