The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Feb. 27, 2017
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Jahun Koo, Asan-si, KR;

Haksun Kim, Seoul, KR;

Kyung-Hun Lee, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-Si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 5/18 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/3674 (2013.01); G09G 3/3688 (2013.01); G09G 3/3696 (2013.01); G09G 5/18 (2013.01); G09G 2300/0417 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/043 (2013.01); G09G 2330/021 (2013.01); G09G 2330/025 (2013.01);
Abstract

A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.


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