The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Nov. 30, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Etai Adar, Yokneam Illit, IL;

Lakshminarayana B. Arimilli, Austin, TX (US);

Yiftach Benjamini, Givat Ela, IL;

Bartholomew Blaner, Shelburne, VT (US);

William J. Starke, Round Rock, TX (US);

Jeffrey A. Stuecheli, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0815 (2016.01); G06F 12/1081 (2016.01); G06F 13/16 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/1081 (2013.01); G06F 13/1668 (2013.01); G06F 12/145 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/621 (2013.01); G06F 2212/656 (2013.01);
Abstract

Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.


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