The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

May. 23, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Satish Raj, San Diego, CA (US);

Shiva Ram Chandrasekaran, San Diego, CA (US);

Li Qiu, Palo Alto, CA (US);

Arun Tyagi, San Diego, CA (US);

Mathew Philip, San Francisco, CA (US);

Rajesh Verma, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/28 (2006.01); G06T 1/20 (2006.01); G06F 17/50 (2006.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01); H01L 27/118 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 1/28 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06T 1/20 (2013.01); H01L 23/525 (2013.01); H01L 23/5286 (2013.01); G06F 2217/78 (2013.01); G06T 2200/28 (2013.01); H01L 27/0207 (2013.01); H01L 2027/11881 (2013.01);
Abstract

A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.


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