The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Dec. 10, 2018
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Yan Li, Morganville, NJ (US);

Jie Lai, Belle Mead, NJ (US);

Hongwei Kong, Basking Ridge, NJ (US);

Kamesh Medapalli, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); H04L 1/00 (2006.01); H03M 13/09 (2006.01); H04L 27/20 (2006.01); H04W 4/80 (2018.01);
U.S. Cl.
CPC ...
H04L 1/0083 (2013.01); H03M 13/09 (2013.01); H04L 1/0054 (2013.01); H04L 1/0061 (2013.01); H04L 27/2017 (2013.01); H04W 4/80 (2018.02);
Abstract

A communication system and method are disclosed for parallel processing of received signals to improve sensitivity of the system. Generally, the method includes demodulating a modulated signal in a first demodulator circuit and a second demodulator circuit in parallel. The first and second demodulated signals are then de-whitened, and a cyclic redundancy code (CRC) check performed on each. If the de-whitened first demodulated signal passes the CRC check a first packet included in the signal is sent to a central processing unit (CPU) for further processing. If the de-whitened second demodulated signal passes the CRC check, and the de-whitened first demodulated signal fails, a second packet included in the de-whitened second demodulated signal is transmitted to the CPU for further processing. In one embodiment, one of demodulator circuits is a GFSK demodulator operated in the phase domain and configured to use maximum likelihood sequence estimation. Other embodiments are also described.


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