The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Aug. 13, 2018
Applicants:

Jack R. Powell, Iii, Los Angeles, CA (US);

Alexander L. Braun, Baltimore, MD (US);

Inventors:

Jack R. Powell, III, Los Angeles, CA (US);

Alexander L. Braun, Baltimore, MD (US);

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/195 (2006.01); G06N 99/00 (2019.01); H03K 19/177 (2006.01); G11C 11/44 (2006.01); H01L 39/02 (2006.01); H03M 7/00 (2006.01); B82Y 10/00 (2011.01); G06N 10/00 (2019.01);
U.S. Cl.
CPC ...
H03K 19/195 (2013.01); B82Y 10/00 (2013.01); G06N 10/00 (2019.01); G11C 11/44 (2013.01); H01L 39/025 (2013.01); H03K 19/17708 (2013.01); H03K 19/1952 (2013.01); H03K 19/1954 (2013.01); H03M 7/003 (2013.01);
Abstract

Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.


Find Patent Forward Citations

Loading…