The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2019
Filed:
Jun. 28, 2017
Applicant:
Hewlett Packard Enterprise Development Lp, Houston, TX (US);
Inventors:
Dacheng Zhou, Fort Collins, CO (US);
Daniel Alan Berkram, Fort Collins, CO (US);
Ryan Barnhill, Fort Collins, CO (US);
Christopher Allan Poirier, Fort Collins, CO (US);
Christopher Wilson, Fort Collins, CO (US);
Assignee:
Hewlett Packard Enterprise Development LP, Houston, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); G06F 17/10 (2006.01); B62D 5/04 (2006.01); H03M 1/48 (2006.01); H03F 1/02 (2006.01); G01S 1/00 (2006.01); H03M 1/64 (2006.01); H03K 5/24 (2006.01); H03F 3/45 (2006.01); H03K 19/20 (2006.01); G01D 5/20 (2006.01); H03M 9/00 (2006.01); H04L 25/03 (2006.01);
U.S. Cl.
CPC ...
H03K 5/24 (2013.01); G01D 5/204 (2013.01); H03F 3/45479 (2013.01); H03K 19/20 (2013.01); H03M 9/00 (2013.01); H04L 25/03076 (2013.01);
Abstract
A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.