The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Mar. 28, 2013
Applicant:

Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;

Inventor:

Tatsuo Nakagawa, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); H03K 5/133 (2014.01); H03H 19/00 (2006.01); H03H 11/26 (2006.01); G11C 27/02 (2006.01); A61B 8/00 (2006.01); G11C 27/00 (2006.01); G01S 7/52 (2006.01); G01S 15/89 (2006.01); G10K 11/34 (2006.01);
U.S. Cl.
CPC ...
H03K 5/133 (2013.01); A61B 8/4494 (2013.01); A61B 8/54 (2013.01); G01S 7/5208 (2013.01); G01S 7/52025 (2013.01); G01S 15/8927 (2013.01); G10K 11/346 (2013.01); G11C 27/00 (2013.01); G11C 27/024 (2013.01); H03H 11/265 (2013.01); H03H 19/00 (2013.01); H03K 2005/00019 (2013.01);
Abstract

A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals.


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