The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Feb. 20, 2017
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Hideyuki Nakamizo, Tokyo, JP;

Morishige Hieda, Tokyo, JP;

Hiroyuki Mizutani, Tokyo, JP;

Kenichi Tajima, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); H03L 7/23 (2006.01); H03L 7/197 (2006.01); H03K 5/00 (2006.01); H03M 7/32 (2006.01);
U.S. Cl.
CPC ...
H03K 5/01 (2013.01); H03L 7/1976 (2013.01); H03L 7/23 (2013.01); H03K 2005/00013 (2013.01); H03K 2005/00286 (2013.01); H03M 7/3028 (2013.01);
Abstract

A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.


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