The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Jul. 07, 2015
Applicant:

Denso Corporation, Kariya, Aichi-pref., JP;

Inventors:

Masakiyo Sumitomo, Kariya, JP;

Shigeki Takahashi, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 27/04 (2006.01); H01L 27/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/861 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 27/04 (2013.01); H01L 27/0635 (2013.01); H01L 29/0804 (2013.01); H01L 29/0821 (2013.01); H01L 29/0834 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/66348 (2013.01); H01L 29/78 (2013.01); H01L 29/8613 (2013.01); H01L 29/0696 (2013.01);
Abstract

A semiconductor device includes: a drift layer; a base layer on the drift layer; a collector layer and a cathode layer opposite to the base layer; multiple trenches penetrating the base layer; a gate electrode in each trench; an emitter region in a surface portion of the base layer and contacting each trench; a first electrode connected to the base layer and the emitter region; and a second electrode connected to the collector layer and the cathode layer. The gate electrodes in a diode region of a semiconductor substrate are controlled independently from the gate electrodes in the IGBT region. A voltage not forming an inversion layer in the base layer is applied to the gate electrodes in the diode region.


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