The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Mar. 25, 2016
Applicant:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Inventors:

Jong Min Jang, Ansan-si, KR;

Jong Hyeon Chae, Ansan-si, KR;

Joon Sup Lee, Ansan-si, KR;

Daewoong Suh, Ansan-si, KR;

Hyun A. Kim, Ansan-si, KR;

Won Young Roh, Ansan-si, KR;

Min Woo Kang, Ansan-si, KR;

Assignee:

SEOUL VIOSYS CO., LTD., Ansan-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/08 (2010.01); H01L 33/38 (2010.01); H01L 33/62 (2010.01); H01L 27/15 (2006.01); H01L 33/20 (2010.01); H01L 33/44 (2010.01);
U.S. Cl.
CPC ...
H01L 27/153 (2013.01); H01L 27/156 (2013.01); H01L 33/20 (2013.01); H01L 33/387 (2013.01); H01L 33/44 (2013.01); H01L 33/62 (2013.01);
Abstract

A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.


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